Adesto and Cadence collaborate to reduce IoT latency
October 2, 2019
Californian companies Adesto Technologies and Cadence Design Systems have collaborated to expand the ecosystem around the xSPI expanded serial peripheral interface communication protocol to enable higher transfer rates and lower latency for flash memory in IoT devices.
Flash memory devices in IoT systems require increasingly higher transfer rates and lower latency, especially as these products frequently run code-intensive wireless stacks and support local artificial intelligence (AI) processing.
Expanding the flash SPI accesses from the traditional four IOs (quad SPI) to eight IOs (octal SPI) with the xSPI serial synchronous protocol increases the serial NOR flash throughput and provides a more efficient method for emerging applications.
The Cadence memory model for xSPI is a commercially available model that lets users ensure optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto’s EcoXiP octal xSPI non-volatile memory (NVM).
“Support for new protocols, such as xSPI, is critical for standard adoption and will help enable a new class of IoT devices,” said David Peña, verification IP product management director at Cadence. “Cadence worked closely with Adesto and other Jedec members to drive development of the xSPI standard, and we’ve broadened our collaboration to facilitate ecosystem development. The availability of the memory model for Adesto’s EcoXiP and host controller design IP for xSPI devices enables joint customers to quickly and easily adopt xSPI while developing their products.”
One of the first NOR flash devices to support xSPI, Adesto’s EcoXiP NVM eliminates the need for expensive on-chip embedded flash in a broad range of emerging IoT applications. It is said to hit the sweet spot for power, system cost and performance, with lower power consumption compared with other octal devices, and offers higher performance than quad SPI devices.
“Moving intelligence to the edge can provide significant advantages, but heavier local processing means that architects must revisit their system’s memory architecture,” said Gideon Intrater, Adesto’s CTO. “XSPI makes it easier for system designers to reap the benefits of octal devices like EcoXiP for smarter, more efficient and user-friendly designs. The new Cadence memory model will help our EcoXiP customers to have even more optimised systems.”
The Cadence memory model for xSPI is part of the Cadence Verification Suite and is optimised for Xcelium parallel logic simulation, along with supported third-party simulators. The suite is comprised of core engines and verification fabric technologies that support the Cadence Intelligent System Design strategy, enabling SoC design.